FIG. 1 is a block diagram illustrating the chip layout of a semiconductor memory device according to the prior art. In particular, the chip layout of FIG. 1 is disclosed in U.S. Pat. No. 5,627,792, entitled "LOC Type Semiconductor Memory Device", issued on May 6, 1997, the disclosure of which is incorporated herein by reference.
The semiconductor memory device is formed on a semiconductor chip 1, and includes four memory cell blocks 10T, 10B, 11T and 11B. Each of memory cell blocks 10T, 10B, 11T and 11B includes a plurality of memory cells (not shown). During the normal operation of the semiconductor memory device (e.g., during an external accessing), a one-bit memory cell is selected in each of memory cell blocks 10T, 10B, 11T and 11B, and data is written/read to/from each of memory cell blocks 10T, 10B, 11T and 11B.
Circuits 12, 14 and 16 are arranged in a center region of the semiconductor chip 1 (that is, the region between cell memory blocks 10T and 10B and memory cell blocks 11T and 11B). The circuits 12, 14 and 16 each have a plurality of pads and buffers for inputting and outputting signals. Such a structure in which pads are arranged in the center region of the chip is referred to as a lead on chip (LOC) arrangement. In a LOC arrangement, the tips of a lead frame are arranged on the chip, and the lead frame is connected at the respective tips to the pads arranged in the center region of the chip by wire bonding. Alignment of the pads in the chip center region allows the area occupied by the pads to be reduced in comparison to a structure in which the pads are arranged at a peripheral portion along both sides of semiconductor chip 1. Thus, the former arrangement improves the efficiency of the semiconductor chip 1.
Generally, a semiconductor memory device having a relatively low density is packed using a package which has a pin layout of an ODIC (Outer-DQ-Inner-Control) type, which is used as a JEDEC standard. In the pin layout of the ODIC type package, data input/output pins are arranged outside of both sides of the package, and address and control pins are arranged inside of the data input/output pins. Although the data input/output pins are arranged outside of both sides thereof, skewing between the data input/output pins does not occur because of the small package.
However, as the integrity density increases and access time is shortened, a skew between signals corresponding to the pins having the same function with respect to each other (for example, between data input/output pins) may occur in the case of the ODIC type package. To prevent such a problem, a NON-ODIC (Non-Outer-DQ-Inner-Control) package type may be used. In the case when memory devices are packed using the NON-ODIC type package, pins having the same function are collectively arranged at an adjacent region to minimize the skew between the signals corresponding to those pins.
Typically, to simplify package bonding, the pads formed on the semiconductor chip are arranged with the same layout as the package. In particular, if a semiconductor memory device is packed using a package having the ODIC type pin layout, the pads formed on the semiconductor chip may be aligned by the ODIC type. Similarly, if a semiconductor memory device is packed using a package having the NON-ODIC type pin layout, the pads formed on the semiconductor chip may be arranged in conformance with the NON-ODIC type pin layout.
In the case of a semiconductor memory device having an ultrahigh density (e.g., a device having a 1 giga-bit capacity), the overall speed of the device may decrease when the data input/output, address signal and control signal pads are arranged in accordance with the pad arrangement method described above. In particular, in FIG. 1, when data is written/read to/from the memory cell blocks 10T and 10B and the memory cell blocks 11T and 11B, data line 15 (or data transmission/reception path) between the data input/output circuits 16 and the memory cell blocks 10T and 10B is larger in length than that between the data input/output circuits 16 and the memory cell blocks 11T and 11B. That is, resistance and capacitance of the data line corresponding to the memory cell blocks 10T and 10B are far larger than those of the data line corresponding to the memory cell blocks 11T and 11B. The signal propagation delay in the former case is larger than in the latter case, thus increasing the access time in the former case. In particular, the time period from which data read out from the memory cell blocks 10T and 10B appears at corresponding data input/output pads is delayed on the basis of the time period from which data read out from the memory cell blocks 11T and 11B appears at corresponding data input/output pads.
As a result, since the data out timing of the semiconductor memory device is determined by the delayed data out time period, it is difficult to realize an ultrahigh density memory device which is implemented in accordance with the pin arrangement method set forth above and is capable of performing a high-speed access operation.